Several challenges still remain for large scale integration of field-effect semiconductor devices. As FET transistor gate lengths continue to scale down, the processes to define them are increasingly difficult to control in order to achieve the desired critical dimensions.
Today, in the field of silicon based FET transistor devices, a self-aligned silicide process is usually included to reduce the resistance of the S/D regions and silicon gates. It typically comprises a preclean process, a metal deposition process and an anneal process to form a metal silicide alloy, followed by a wet selective etch to remove the non-reacted metal. During such a wet etch process, any exposed silicon surface (e.g. a silicon channel layer) automatically forms a thin passivating silicon oxide at its surface, protecting the underlying silicon from being affected.
When manufacturing germanium based FET transistors, e.g., on a germanium substrate, a similar germanidation process has been developed in the state of the art. Here, void formation is a major issue when applying a germanidation process straight on a germanium surface. Such a germanidation process typically comprises a preclean process, a metal deposition process and an anneal process to form a metal germanide alloy, followed by a wet selective etch to remove the non-reacted metal. While the annealing temperature can be optimized to eliminate void formation caused by diffusion of Ge into the metal (e.g. Ni or NiPt) during the germanidation reaction itself (see for instance in U.S. Pat. No. 7,517,765), voids can still be formed during the selective etch for removing the non-reacted metal, which may be problematic.